A high-performance buffer for non-volatile memories

Author

De Ambrogi, L. ; Nicosia, S. ; Pagano, G. ; Palumbo, G.

Author_Institution

ST-Microelectron., Catania, Italy

Volume

2

fYear

2002

fDate

2002

Firstpage

611

Abstract

In this paper, a CMOS data output buffer is proposed. The buffer shows high-speed performance together low noise characteristics. The performance is achieved by implementing a precharging of the output load. The buffer was developed with a 0.35 μm CMOS technology and a 3.3 V power supply. Eldo simulations have been used to validate its features, and a delay lower than 3 ns with a voltage noise of about 300 mV was found.

Keywords

CMOS logic circuits; buffer circuits; circuit CAD; circuit simulation; delays; high-speed integrated circuits; integrated circuit design; integrated circuit modelling; integrated circuit noise; logic CAD; logic simulation; random-access storage; 0.35 micron; 3 ns; 3.3 V; 300 mV; CMOS high-speed low-noise buffers; buffer delay times; buffer power supply voltage; buffer voltage noise level; high-performance data output buffers; nonvolatile memories; output load precharging; CMOS technology; Capacitance; Circuit noise; Integrated circuit noise; Noise reduction; Nonvolatile memory; Phased arrays; Power supplies; Rails; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2002. 9th International Conference on

Print_ISBN

0-7803-7596-3

Type

conf

DOI

10.1109/ICECS.2002.1046243

Filename

1046243