Title :
Experimental results of an optimised voltage tripler
Author :
Zhang, M. ; Llaser, N.
Author_Institution :
Inst. d´´Electron. Fondamentale, Univ. de Paris-Sud, Orsay, France
Abstract :
In this paper, experimental results of a voltage tripler are given. This voltage tripler is improved against the influence of parasitic capacitances on output voltage and optimised in terms of its die area. The interaction between working frequency and die area is discussed. The operation of the voltage tripler in terms of low supply voltage is also investigated. The test results confirm theoretical prediction of the output voltage improvement and the minimisation of die area by design optimisation.
Keywords :
capacitance; circuit optimisation; integrated circuit design; integrated circuit measurement; low-power electronics; voltage multipliers; design optimisation; die area minimisation; low supply voltage operation; optimised voltage tripler; output voltage; parasitic capacitance; voltage tripler test; working frequency; Capacitors; Charge pumps; Degradation; Design optimization; Equivalent circuits; Frequency; Low voltage; Parasitic capacitance; Stacking; Testing;
Conference_Titel :
Electronics, Circuits and Systems, 2002. 9th International Conference on
Print_ISBN :
0-7803-7596-3
DOI :
10.1109/ICECS.2002.1046247
