Application of adaptive evolutionary algorithm for low power design of CMOS digital circuits

This paper introduces a high-level synthesis method, based on an adaptive evolutionary algorithm, that utilizes an ´as soon as possible´ (ASAP) scheduling algorithm to reduce the switching power of CMOS circuits. Experimental verification of the algorithm has been performed for a set of test circuits chosen from ISCAS´85 and ISCAS´89 benchmarks, proving its efficiency. The obtained power consumption reduction varies for different benchmarks from 3 to 42 percent, without deteriorating the throughput of the whole system. Allowing deterioration of the throughput by 10 to 50 percent, the power reduction can be even larger (up to 52 percent).