Efficient post-layout timing verification via RLC trees and explicit PWL timing integration

An approach to sub-micron VLSI timing verification is presented. VLSI signal paths are split into typical stages, each composed of a driver, interconnect circuitry and loading. The timing model for the interconnections is based on an RLC tree, and the CMOS drivers are represented by piecewise constant (PWC) transistor models, which suit well the fast timing analysis technique used, i.e. explicit piecewise linear (PWL) integration. In addition, coupling capacitances to the neighboring lines can be incorporated into the RLC tree. The equivalent second order approximations for the RLC tree are derived by moment matching. Those models reduce significantly the order of the problem, and provide thereby substantial CPU-time savings when simulated. They are also shown to be accurate enough to model the timing behavior of a stage. Practical examples included in the paper verify the presented approach.