High-speed receivers for on-chip interconnections in deep-submicron process

Author

Huang, Hong-Yi ; Chen, Shih-Lun

Author_Institution

Dept. of Electron. Eng., Fu-Jen Univ., Hsin-Chuang, Taiwan

Volume

2

fYear

2002

fDate

2002

Firstpage

769

Abstract

The transient sensitive trigger (TST) was used to improve the RC delay time of the long interconnection in deep sub-micron process. The conventional TST circuit has a threshold voltage drop during transitions which results in a longer delay time. In this work, modified techniques are proposed to improve the drawbacks of the conventional TST. The new versions have 45-74% delay improvement compared to the conventional TST, simulated using a 0.25 μm CMOS process. The proposed circuits can be applied to the receiving of long interconnection signals for high-speed VLSI applications.

Keywords

CMOS logic circuits; RC circuits; circuit simulation; delays; high-speed integrated circuits; integrated circuit design; integrated circuit interconnections; integrated circuit modelling; logic design; logic simulation; transient response; trigger circuits; 0.25 micron; CMOS high-speed receivers; TST; high-speed VLSI applications; interconnection RC delay time improvement; long interconnection signals; on-chip interconnections; transient sensitive triggers; transition threshold voltage drop; CMOS process; Circuit simulation; Delay effects; Dielectric materials; Indium phosphide; Integrated circuit interconnections; Laboratories; Threshold voltage; Very large scale integration; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2002. 9th International Conference on

Print_ISBN

0-7803-7596-3

Type

conf

DOI

10.1109/ICECS.2002.1046283

Filename

1046283