DocumentCode
383792
Title
A MOS transistor model for peak voltage calculation of crosstalk noise
Author
Renault, Patricia ; Bazargan-Sabet, Pirouz ; Le Dû, Dominique
Author_Institution
LIP6, Paris VI Univ., France
Volume
2
fYear
2002
fDate
2002
Firstpage
773
Abstract
To certify the correctness of a design, in deep submicron technologies, the verification process has to cover some new issues. The noise introduced on signals through the crosstalk coupling is one of these emerging problems. In this paper, we expose a first model to evaluate the peak value of the noise injected on a signal during the transition of its neighboring signals. Then, analysing the error introduced by each step of simplification in this model, we propose a new MOS transistor model.
Keywords
MOSFET; circuit simulation; crosstalk; integrated circuit modelling; integrated circuit noise; semiconductor device models; semiconductor device noise; MOS transistor model; crosstalk coupling; crosstalk noise; deep submicron technologies; design verification process; model simplification errors; peak injected signal noise; peak voltage calculation; signal transition; Capacitance; Circuit noise; Coupling circuits; Crosstalk; Delay; Error analysis; MOSFETs; Steady-state; Voltage; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits and Systems, 2002. 9th International Conference on
Print_ISBN
0-7803-7596-3
Type
conf
DOI
10.1109/ICECS.2002.1046284
Filename
1046284
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