DocumentCode
383800
Title
A comparison of precharge policies with modern DRAM architectures
Author
Alakarhu, Juha ; Niittylahti, Jarkko
Author_Institution
Inst. of Digital & Comput. Syst., Tampere Univ. of Technol., Finland
Volume
2
fYear
2002
fDate
2002
Firstpage
823
Abstract
The imbalance between the processor and memory speeds makes memory system design an increasingly important task. This paper evaluates one of the basic design issues of a DRAM memory system: selecting the precharge policy. Open and closed page policies are compared using different applications, cache systems, and DRAM architectures. The results show that the open page policy generally leads to 10%-20% better result than the closed page policy. This paper also shows that increasing the cache size reduces the advantage of the open page policy. Finally, one can see that increasing the number of DRAM banks improves a memory system´s ability to utilize the open page policy and the locality in the access stream.
Keywords
DRAM chips; cache storage; circuit simulation; logic CAD; logic simulation; memory architecture; paged storage; storage management; DRAM architecture precharge policy comparison; DRAM bank number; DRAM memory systems; access stream locality; cache size; cache systems; closed page policies; memory system design; open page policies; processor/memory speed imbalance; Computer architecture; Control systems; Delay; Guidelines; Random access memory;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits and Systems, 2002. 9th International Conference on
Print_ISBN
0-7803-7596-3
Type
conf
DOI
10.1109/ICECS.2002.1046301
Filename
1046301
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