Title :
SOI SRAM design advances & considerations
Author :
Natarajan, Sreedhar ; Marshall, Andrew
Author_Institution :
ATMOS Corp., Ottawa, Ont., Canada
Abstract :
SOI is a relatively new introduction in memory design and its use can improve performance. Bit-line capacitance and pass gate loads are major sources of current discharge in SOI SRAM cells. Currents from bit line capacitance and cell leakage can corrupt the cell data. SOI improves the soft error rate due to Alpha particles, mainly because of the presence of buried oxide. This paper is a brief tutorial on SOI SRAM design issues, leakages and soft error rates.
Keywords :
CMOS memory circuits; SRAM chips; alpha-particle effects; buried layers; capacitance; error statistics; integrated circuit design; integrated circuit reliability; leakage currents; logic design; low-power electronics; silicon-on-insulator; Alpha particle effects; CMOS; SOI SRAM design; Si-SiO2; bit-line capacitance; buried oxide; cell data corruption; cell leakage; current discharge sources; leakage currents; low power RAM technology; low voltage operation; pass gate loads; soft error rate; Capacitance; Error analysis; Fault location; Flip-flops; Instruments; Low voltage; MOS devices; Packaging; Random access memory; Read-write memory;
Conference_Titel :
Electronics, Circuits and Systems, 2002. 9th International Conference on
Print_ISBN :
0-7803-7596-3
DOI :
10.1109/ICECS.2002.1046304
