Shadowed register cell for skew-resistant timing

A shadowed register cell with controllable latency for synthesis of synchronous systems with large clock skewing is presented. Arbitrary delays in clock distribution allow peak supply current reduction in a much wider range than is possibly achieved by means of standard registers. This is put in use to trade clock cycle time for I*R voltage drops and switching noise shaping in mixed analogue-digital systems. The proposed C²MOS cell structure has been implemented with less than 20% area and power overhead compared to the standard register.