Title :
n-Channel MOSFETs Fabricated on SiGe Dots for Strain-Enhanced Mobility
Author :
V. Jovanovi?;C. Biasotto;L. K. Nanver;J. Moers;D. Gr?tzmacher;J. Gerharz;G. Mussler;J. van der Cingel;J. J. Zhang;G. Bauer;O. G. Schmidt;L. Miglio
Author_Institution :
Delft Institute of Microsystems and Nanoelectronics, Delft University of Technology, Delft, The Netherlands
Abstract :
The silicon germanium dots grown in the Stranski-Krastanow mode are used to induce biaxial tensile strain in a silicon capping layer. A high Ge content and correspondingly high Si strain levels are reached due to the 3-D growth of the dots. The n-channel MOS devices, referred to in this letter as DotFETs, are processed with the main gate segment above the strained Si layer on a single dot. To prevent the intermixing of the Si/SiGe/Si structure, a novel low-temperature FET structure processed below 400°C has been implemented: The ultrashallow source/drain junctions formed by excimer-laser annealing in the full-melt mode of ion-implanted dopants are self-aligned to a metal gate. The crystallinity of the structure is preserved throughout the processing, and compared to reference devices, an average increase in the drain current of up to 22.5% is obtained.
Keywords :
"Silicon","Silicon germanium","Logic gates","Strain","Annealing","Junctions","Fabrication"
Journal_Title :
IEEE Electron Device Letters
DOI :
10.1109/LED.2010.2058995