Title :
On the impact of technology scaling on mixed PTL/static circuits
Author :
Cho, Geun Rae ; Chen, Tom
Author_Institution :
Dept. of Electr. & Comput. Eng., Colorado State Univ., Fort Collins, CO, USA
Abstract :
We present the impact of technology scaling on mixed PTL/static circuits and compare the results with that of domino and conventional static CMOS. The state-of-the-art technologies of 0.18 μm, 0.13 μm, and 0.1 μm were used in the study with Vdd being scaled accordingly. The benchmark suite consists of 10 circuits of varying complexities and they are actual circuits used in a state-of-the-art 64-bit microprocessor in the form of either dynamic or static CMOS circuits. The objective of this work is to determine how performance and power consumption scales with technology scaling. Our experimental results show that the mixed PTL/static circuit style is a promising alternative in power and power-delay product while achieving comparable delay to the dynamic circuit style.
Keywords :
CMOS logic circuits; circuit complexity; integrated circuit design; integrated circuit testing; logic design; logic testing; low-power electronics; microprocessor chips; 0.1 micron; 0.13 micron; 0.18 micron; 64 bit; circuit complexity; delay; domino circuits; dynamic CMOS circuits; microprocessor; mixed PTL/static circuits; pass-transistor logic; power consumption; power-delay product; static CMOS circuits; technology scaling; voltage scaling; CMOS logic circuits; CMOS technology; Circuit optimization; Delay; Energy consumption; Microprocessors; Systems engineering and theory; Vehicle dynamics; Vehicles; Very large scale integration;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 2002. Proceedings. 2002 IEEE International Conference on
Print_ISBN :
0-7695-1700-5
DOI :
10.1109/ICCD.2002.1106789
