Speculative trace scheduling in VLIW processors

Author

Agarwal, Mohini ; Nandy, S.K.

Author_Institution

Indian Inst. of Sci., Bangalore

fYear

2002

fDate

2002

Firstpage

408

Lastpage

413

Abstract

VLIW processors are statically scheduled processors and their performance depends on the quality of schedules generated by the compiler\´s scheduler. We propose a new scheduling scheme where the application is first divided into decision trees and then further split into traces. Traces are speculatively scheduled on the processor based on their probability of execution. We have developed a tool "SpliTree" to generate traces automatically. By using dynamic branch prediction for scheduling traces our scheme achieves approximately 1.4× performance improvement over that using decision trees for Spec92 benchmarks simulated on TriMedia™.

Keywords

decision trees; parallel architectures; performance evaluation; processor scheduling; program compilers; virtual machines; Spec92 benchmarks; SpliTree tool; Trimedia; VLIW processors; automatic trace generation; compiler scheduler; decision trees; dynamic branch prediction; execution probability; scheduling scheme; speculative trace scheduling; statically scheduled processors; Computer aided instruction; Decision trees; Laboratories; Optimizing compilers; Processor scheduling; Tail; VLIW;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 2002. Proceedings. 2002 IEEE International Conference on

ISSN

1063-6404

Print_ISBN

0-7695-1700-5

Type

conf

DOI

10.1109/ICCD.2002.1106803

Filename

1106803