DocumentCode
385661
Title
Embedded protocol processor for fast and efficient packet reception
Author
Henriksson, Tomas ; Nordqvist, Ulf ; Liu, Dake
Author_Institution
Dept. of Electr. Eng., Linkoping Univ., Sweden
fYear
2002
fDate
2002
Firstpage
414
Lastpage
419
Abstract
Computer network equipment presents a bottleneck for further increasing the capacity in the networks. Terminals have problems keeping up with network speed when using general purpose processors for protocol processing. We present a novel processor architecture, that works in-line with the data flow and does not use a traditional von Neuman architecture. The program is contained in three lookup tables within the processor core, which allows for one cycle if-then-else and switch-case-case... execution. The processor is estimated to be able to handle a 10 Gb/s Ethernet connection when implemented in 0.18 micron technology.
Keywords
computer architecture; local area networks; protocols; table lookup; 0.18 micron; 10 Gbit/s; Ethernet connection; computer network equipment; data flow; embedded protocol processor; fast efficient packet reception; lookup tables; one cycle if-then-else execution; one cycle switch-case-case execution; processor architecture; processor core; Application software; Computer interfaces; Computer networks; Ethernet networks; Microcontrollers; Network interfaces; Payloads; Physical layer; Protocols; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design: VLSI in Computers and Processors, 2002. Proceedings. 2002 IEEE International Conference on
ISSN
1063-6404
Print_ISBN
0-7695-1700-5
Type
conf
DOI
10.1109/ICCD.2002.1106804
Filename
1106804
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