Design of a novel 3.3 V CMOS logarithmic amplifier with a two step linear limiting architecture

In this paper, we discuss the VLSI design of a logarithmic amplifier (LA) for wide dynamic range and high sensitivity radar systems. In general, an LA consists of an input stage, a logarithmic stage, and an output stage. In order to give a much wider dynamic range and a higher speed than the conventional LA, a new type of two-step linear limiting architecture is proposed in the logarithmic stage. Two kinds of simple attenuators, designed with resistors, and a 30 dB middle amplifier are inserted in the middle of the proposed architecture to reduce the complexity and to increase the input dynamic range. It is fabricated on the basis of 0.35 μm standard CMOS technology. The effective chip area is 1310 μm×1540 μm, and shows a power consumption of 90 mW at 3.3 V supply voltage. Through simulation and measurements, it is verified that it shows the characteristics of 72 dB dynamic range and 50 ns pulse response.