• DocumentCode
    385834
  • Title

    On three-dimensional layout of pyramid networks

  • Author

    Yamada, Toshinori ; Fujii, Naotaka ; Ueno, Shuichi

  • Author_Institution
    Dept. of Commun. & Integrated Syst., Tokyo Inst. of Technol., Japan
  • Volume
    1
  • fYear
    2002
  • fDate
    2002
  • Firstpage
    159
  • Abstract
    Pyramid networks are well-known as suitable structures for parallel computations such as image processing. This paper shows a practical 3D VLSI layout of the N-vertex pyramid network with volume O(N) and wire-length O(3√N). Since the known best lower bounds for the volume and wire-length of a 3D layout for an N-vertex pyramid network are Ω(N) and Ω(3√N/log N), respectively, the volume of our layout is optimal, and the wire-length of our layout is close to the optimal.
  • Keywords
    VLSI; circuit CAD; circuit optimisation; integrated circuit interconnections; integrated circuit layout; integrated circuit modelling; 3D grid embedded graphs; N-vertex pyramid network volume; VLSI 3D pyramid network layout; VLSI circuits; circuit optimization; image processing; network wire-length; parallel computation pyramid network structures; volume/wire-length lower bounds; Circuits; Computer networks; Concurrent computing; Costs; Image processing; Joining processes; Very large scale integration; Volume measurement;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2002. APCCAS '02. 2002 Asia-Pacific Conference on
  • Print_ISBN
    0-7803-7690-0
  • Type

    conf

  • DOI
    10.1109/APCCAS.2002.1114928
  • Filename
    1114928
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=385834