A rapid prototyping embedded system platform and its HW/SW communication interface generation and verification

In this paper, we first present a DSP+FPGA rapid prototyping system platform (RAPSP) capable of implementing and emulating various embedded systems based on HW/SW codesign. We secondly present the system design flow and the verification methodology of the platform. To facilitate the communication efficiency between the DSP (SW section) and the FPGA arrays (HW section), communication buffers are employed. A library of parameterized communication interface modules was also developed to support the HW/SW communication designs on the platform. Transaction level simulation models were developed so that DSP and FPGA designs can be verified together. A practical system design/verification flow is also developed. Finally, an LD-CELP speech compression system implementation example on RAPSP is described.