A bus arbitration scheme for HDTV decoder SoC

A bus arbitration scheme for a HDTV (high-definition television) decoder system-on-a-chip (SoC) is described in this paper. The bus arbitration scheme is designed to utilize the bus bandwidth efficiently in order to reduce the amount of internal data buffers, while assuring the required real time performance. The introduced time sliced arbitration scheme is a feasible bus arbitration solution to such a heterogeneous system as the HDTV decoder SoC. The synchronization control of the HDTV decoding process is partly incorporated into the bus arbitration scheme. The efficiency of the bus arbitration scheme is verified by system level hardware/software co-simulation.