• DocumentCode
    3861397
  • Title

    A CMOS K-winners-take-all circuit with O(n) complexity

  • Author

    B. Sekerkiran;U. Cilingiroglu

  • Author_Institution
    ASIC Design Center, Istanbul Tech. Univ., Turkey
  • Volume
    46
  • Issue
    1
  • fYear
    1999
  • Firstpage
    1
  • Lastpage
    5
  • Abstract
    Design and implementation of a CMOS K-winners-take-all circuit are presented. The proposed architecture is of O(n) complexity and enables the number of winners to be determined before each competition phase by adjusting the current ratio of two current sources. A 10-cell test chip has been designed and fabricated in a 3 /spl mu/m CMOS process. Functionality has been verified by testing. The simple structure of the circuit is highly suitable for analog VLSI implementations.
  • Keywords
    "Voltage","Circuit testing","Capacitance","Tail","CMOS process","Very large scale integration","Neural networks","Signal processing algorithms","Filtering","Genetic algorithms"
  • Journal_Title
    IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
  • Publisher
    ieee
  • ISSN
    1057-7130
  • Type

    jour

  • DOI
    10.1109/82.749038
  • Filename
    749038
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3861397