Divergent Branch Threads Compaction for Efficient SIMD Control Flow

Wide Single instruction multiple data (SIMD) architectures are very important in the computeintensive applications. The SIMD execution model is inefficient when it suffers from the divergent control flow. The divergent execution paths across loop iterations take place sequentially on SIMD, which defeats part of the efficiency advantage of SIMD execution. This paper proposes a mechanism to compact the divergent branch threads to mitigate the impact of branch thread divergence on SIMD architectures. It relaxes the SIMD execution model by allowing the distinct instruction flows to be scheduled independently, instead of one single instruction flow. It increases flexibility and mitigates the synchronization cost of co-issuing instructions from different divergent branch threads by giving the Vector processing elements (VPEs) the ability to direct their own control flow. The proposed divergent branch threads compaction mechanism improves performance by 2.56x over traditional SIMD architecture for a wide variety of general purpose parallel applications while the area overhead only increases 6.48%.