• DocumentCode
    3861537
  • Title

    Tuning logic simulators for timing analysis

  • Author

    D.M. Maksimovic;V.B. Litovski

  • Author_Institution
    Fac. of Electron. Eng., Nis Univ., Serbia
  • Volume
    35
  • Issue
    10
  • fYear
    1999
  • fDate
    5/13/1999 12:00:00 AM
  • Firstpage
    800
  • Lastpage
    802
  • Abstract
    An original method for digital circuit delay estimation within a logic simulator framework and HDL modelling mechanism needed for its implementation are proposed. The method is implemented using the simulator Alecsis and its efficiency is demonstrated on a set of ISCAS´85 benchmark circuits.
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19990545
  • Filename
    771427
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3861537