Title :
A 12-b digital-background-calibrated algorithmic ADC with -90-dB THD
Author :
O.E. Erdogan;P.J. Hurst;S.H. Lewis
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA
Abstract :
An analog queue-based architecture and an adaptive digital-calibration algorithm calibrate a 12-b algorithmic analog-to-digital converter in the background. At a sampling rate of 125 ksample/s and with monolithic background calibration, the peak signal-to-(noise+distortion) ratio is 71 dB, and the spurious-free dynamic range is 95 dB. The total power dissipation is 16 mW from 5 V. The active area is 5.9 mm/sup 2/ in 1.5-/spl mu/m CMOS.
Keywords :
"Calibration","Interpolation","Polynomials","Analog-digital conversion","Sampling methods","Temperature","Bandwidth","Distortion","Dynamic range","Power dissipation"
Journal_Title :
IEEE Journal of Solid-State Circuits
