Chaos-based random number generators. Part II: practical realization

This paper and its companion (see ibid., vol. 48, p. 281-88, 2001) are devoted to to the analysis of the application of a chaotic piecewise-linear one-dimensional (PL1D) map as Random Number Generator (RNG). In Part I, me have mathematically analyzed the information generation process of a class of PL1D maps. In this paper, we find optimum parameters that give an RNG with lowest redundancy and maximum margin against parasitic attractors. Further, the map is implemented in a 0.8 /spl mu/m standard CMOS process utilizing switched current techniques. Post-layout circuit simulations of the RNG indicate no periodic attractors over variations in temperature, power supply and process conditions, and maximum redundancy of 0.4%. We estimate that the output bit rate of our RNG is 1 Mbit/s, which is substantially higher than the output bit rate of RNGs available on the market.