A pipelined noise shaping coder for fractional-N frequency synthesis

In this paper, we present the design considerations and implementation aspects of a pipelined all-digital fourth-order multi-stage-noise-shaping (MASH) delta-sigma (/spl utri//spl Sigma/) modulator suitable for fractional-N (F-N) phase-locked loop (PLL) frequency synthesis applications. In an effort to reduce the hardware complexity and power consumption, the alignment registers, which are normally required in pipelined adders, are eliminated by taking advantage of static modulator input. The MASH modulator has successfully been targeted to an Altera/sup TM/ field-programmable-gate-array (FPGA) device. The functional operation of the modulator has been verified through structural bit-level simulations as well as experimental results on the actual FPGA implementation.