DocumentCode :
3862596
Title :
A novel high-speed, low-offset, loading condition-adaptable voltage buffer
Author :
Marius Neag;Albert Fazakas;Lelia Festila
Author_Institution :
Technical University of Cluj-Napoca, Romania, Bases of Electronics Department, 26-28 Gh. Bari?iu street, 400027 Cluj-Napoca, Romania, Tel. +40-264-401243, Fax: +40-264-591340
fYear :
2006
Firstpage :
121
Lastpage :
124
Abstract :
This paper proposes several high-speed voltage buffers and an effective method for optimizing their step response. The buffers combine a low offset structure with a signal-dependent biasing technique that results in significant slew-rate enhancement. A set of RC networks provide an effective way of controlling the step-response parameters and ensures input impedance matching. The compensation elements are sized using the PSpice Optimizer, directly in the time domain. A version that allows electronic adjustment in order to optimize the step response under various loading conditions is described, as well. A design example validates the proposed structure and optimization method.
Keywords :
"Voltage","Optimization methods","Operational amplifiers","Linearity","Tin","Radio control","Impedance matching","Negative feedback loops","Bandwidth","Design optimization"
Publisher :
ieee
Conference_Titel :
Applied Electronics, 2006. AE 2006. International Conference on
Print_ISBN :
80-7043-442-2
Type :
conf
DOI :
10.1109/AE.2006.4382980
Filename :
4382980
Link To Document :
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