A novel high-speed, low-offset, loading condition-adaptable voltage buffer

This paper proposes several high-speed voltage buffers and an effective method for optimizing their step response. The buffers combine a low offset structure with a signal-dependent biasing technique that results in significant slew-rate enhancement. A set of RC networks provide an effective way of controlling the step-response parameters and ensures input impedance matching. The compensation elements are sized using the PSpice Optimizer, directly in the time domain. A version that allows electronic adjustment in order to optimize the step response under various loading conditions is described, as well. A design example validates the proposed structure and optimization method.