New mapping model in 2D mesh for Nview multidisplay

Nview Multidisplay technology is getting popular in many fields. In order to allow a high degree of parallel processing, the processing units would be massively replicated on the chip. Traditional bus based architecture faces scalability issue. In this paper, we introduce the concept of network on chip to Nview Multidisplay application. The 2D Mesh topology is explored based on the requirement of Nview Multidisplay. A new mapping model and a mapping algorithm are developed to obtain an optimized placement of the processing units. The results from our simulations under the metrics of end-to-end (ETE) delay and throughput in different offered load are compared with those of traditional mesh topology.