TSV integration with 20nm CMOS technology for 3D-IC enablement

This paper describes the process development of TSV integration with 20nm CMOS technology and device performance characterization for 3D integrated circuit (3DIC) enablement. 6×55um Through-silicon-via (TSV) on 20nm CMOS technology has been developed and demonstrated. Key module process issues, such as V0 high resistance, M1 high leakage and Cu pumping which prevent TSV to be integrated with BEOL through via-middle approach for mobile applications, have been addressed through design of experiments (DOEs) study and process optimization. TSV electrical characterization, TSV´s impact on transistor, analog/digital circuits & BEOL performance considering TSV Keep-out-zone (KOZ) & Cu pumping impact have been intensively investigated and presented in this paper. Cu diffusion & contamination during TSV back side integration, i.e. MEOL process, has also been analyzed and monitored with time of flight-secondary ion mass spectrometry (TOF-SIMs) evaluation. Electrical test results confirm that the optimized process is robust and minimizes the impact of TSV KOZ and Cu pumping on device and BEOL interconnects.