A dynamically reconfigurable logic engine with a multi-context/multi-mode unified-cell architecture

Reconfigurable logic LSIs, such as FPGAs, have been perceived as devices for prototyping and emulation. As the size and speed of FPGAs rapidly increase, however, they have begun to be used in /spl mu/P-based systems as reconfigurable accelerators. The idea is to achieve both hardware efficiency and software programmability by dynamically reconfiguring FPGAs. This idea, reconfigurable computing, provides an attractive solution especially for media/network-centric applications. Various types of reconfiguration scenarios in such applications, however, require logic LSIs to significantly enhance reconfigurability in three respects: (1) agility-reconfiguration may need to take place in very short intervals, say within a hundred /spl mu/P instructions; (2) controllability-reconfiguration may be controlled from an external /spl mu/P or by itself; (3) flexibility-reconfiguration target may be arbitrarily positioned and irregularly shaped. The dynamically reconfigurable logic engine (DRLE) prototype described meets this challenge.