DocumentCode
38665
Title
Variation-Aware Geometric Programming Models for the Clock Network Buffer Sizing Problem
Author
Rakai, Logan ; Farshidi, Amin ; Westwick, David ; Behjat, Laleh
Author_Institution
Dept. of Electr. & Comput. Eng., Univ. of Calgary, Calgary, AB, Canada
Volume
33
Issue
4
fYear
2014
fDate
Apr-14
Firstpage
532
Lastpage
545
Abstract
In this paper, we present and analyze four efficient models that produce significantly improved results by optimizing conflicting power and skew objectives in the clock network buffer sizing problem. Each model is in geometric programming format and has certain advantages, such as maximum reduction in power, robustness to process variation, and striking a balance between skew and power optimization. The buffer sizing problem is formulated as a geometric programming problem to provide globally optimal solutions to the four models. We also show that a geometric programming multiobjective model can be used to optimize both power and skew without requiring any tuning from a designer. The presented self-tuning multiobjective formulation not only provides optimal solutions for buffer sizes, but also finds the tuning parameters that result in overall combined reduction in power and skew without loss of convexity. The effectiveness of the models are illustrated on several publicly available benchmarks. The models provide on average 40% to 60% improvement in power while reducing skew in several cases. We have also proposed a smart heuristic for discretization of the continuous geometric programming solution that preserves skew and power. Finally, we provide a guideline for designers to decide which one of the proposed models is the most appropriate for their needs.
Keywords
circuit optimisation; circuit tuning; clocks; digital integrated circuits; geometric programming; self-adjusting systems; variational techniques; clock network buffer sizing problem; power optimization; self-tuning multiobjective formulation; skew optimization; tuning parameters; variation-aware geometric programming models; Clocks; Delays; Integrated circuit modeling; Mathematical model; Optimization; Programming; Robustness; Clock networks; geometric programming; robust optimization;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/TCAD.2013.2293067
Filename
6774504
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