Title :
APU: specification and design of a multi algorithm ATM policing unit IP
Author :
De Lima, José Antônio Gomes ; Cavalcanti, Antonio Carlos ; De Lucena, Solon Ferreira
Abstract :
Today\´s needs of miniaturization, performance and power consumption of entire "connected" wireless information processing units and time-to-market constraints, impose design strategies that (re)use building IP (intellectual property) blocks with increasing flexibility capabilities. Previous works on ATM layer controllers provided designs of chips/cores of multi/single port single ASIC chips and single FPGA chips that implement several algorithm types, for the entire ATM layer processing, by microinstruction programming only. In order to provide designers with less complex (more reusable) IP for their appliance, this paper presents APU: an IP of a hardware core, designed to execute multi algorithm ATM policing functions only.
Keywords :
application specific integrated circuits; asynchronous transfer mode; circuit simulation; field programmable gate arrays; industrial property; integrated circuit design; integrated circuit modelling; logic CAD; logic simulation; protocols; APU intellectual property specification/design; ATM layer controllers; ATM layer processing algorithms; ATM policing functions; ATM protocol; FPGA; building IP block reuse design strategies; chip/core controller design; connected wireless information processing units; hardware IP cores; microinstruction programming; multi-algorithm ATM policing unit; multi/single port single ASIC chips; Algorithm design and analysis; Application specific integrated circuits; Buildings; Energy consumption; Field programmable gate arrays; Hardware; Home appliances; Information processing; Intellectual property; Time to market;
Conference_Titel :
Integrated Circuits and Systems Design, 2002. Proceedings. 15th Symposium on
Print_ISBN :
0-7695-1807-9
DOI :
10.1109/SBCCI.2002.1137634
