New hardware implementation of parallel 1D FFT

In this paper, we propose a new technique for the parallel implementation of 1D FFT. The paper allocates one two-port memory unit for each butterfly-processing unit. The two output words of the i^th memory module are connected permanently to the inputs of the i^th butterfly processor. The interconnection network used uses a limited number of two-way switches. This layout cancels completely the transposition operation required in all the existing implementations. The address generating system is very simple and results in conflict-free addressing. The proposed system reduces the total processing time and leaves the results in the different memory modules arranged in the natural order that saves another transposition operation normally used with existing systems.