Title :
Neural network implementation on a FPGA
Author :
Chen, YJ ; Du Plessis, WP
Author_Institution :
Pretoria Univ., South Africa
Abstract :
This work implemented a feedforward neural network on a FPGA (field programmable gate array). A study was conducted to find the minimum precision required to maintain a recognition rate of at least 95% for two characters within an optical character recognition application. To reduce the circuit size, the bit serial architecture was realised to perform the arithmetic operation. This resulted in an optimal use of the FPGA resources.
Keywords :
feedforward neural nets; field programmable gate arrays; multilayer perceptrons; neural net architecture; optical character recognition; FPGA; arithmetic operation; bit serial architecture; feedforward neural network; field programmable gate array; multilayer perceptrons; neural network implementation; optical character recognition application; recognition rate; serial-parallel multiplier; Biological neural networks; Character recognition; Feedforward neural networks; Feeds; Field programmable gate arrays; Multi-layer neural network; Network topology; Neural network hardware; Neural networks; Neurons;
Conference_Titel :
Africon Conference in Africa, 2002. IEEE AFRICON. 6th
Print_ISBN :
0-7803-7570-X
DOI :
10.1109/AFRCON.2002.1146859
