Title :
A 30ns-32b programmable arithmetic operator
Author :
Boudon, G. ; Mollier, P. ; Nuez, J. ; Wallart, F.
Author_Institution :
IBM Component Development Laboratory, Borbeil-Essonnes, France
Abstract :
This paper will cover a programmable arithmetic operator implemented in a 6.9×7.1mm gate array chip containing 6000 logic ceils, dissipating less than 1W. The measured gate array is 200ps in a 0.5μm CMOS technology.
Keywords :
Arithmetic; CMOS logic circuits; CMOS technology; Computer aided instruction; Delay; FETs; Power supplies; Random access memory; Read only memory; Wiring;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1987 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1987.1157232
