• DocumentCode
    387062
  • Title

    A 21ns 32K × 8 CMOS SRAM with a selectively pumped P-well array

  • Author

    Wang, Kangping ; Bader, Michael ; Voss, P. ; Soorholtz, V. ; Mauntel, R. ; Mendez, H. ; Kung, R.

  • Author_Institution
    Motorola Memory Products Division, Austin, TX
  • Volume
    XXX
  • fYear
    1987
  • fDate
    - Feb. 1987
  • Firstpage
    254
  • Lastpage
    255
  • Abstract
    A selectivity pumped P-well array used in a 32K×8 CMOS SRAM with a divided-word line block architecture to achieve a 21ns access time, will be described. The chip (6.83×8.97mm) was processed in a 1.2μm double-level metal, twin-well CMOS technology. Active power is 330mW at 22MHz.
  • Keywords
    Asynchronous circuits; CMOS technology; Clamps; Delay; Differential amplifiers; Driver circuits; Impedance; MOS devices; Random access memory; Solid state circuits;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1987 IEEE International
  • Conference_Location
    New York, NY, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1987.1157234
  • Filename
    1157234
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=387062