DocumentCode
387193
Title
A new low-power and area efficient RAKE receiver design without incurring performance degradation
Author
Lee, Hyung Jin ; Ha, Dong Sam
Author_Institution
Dept. of Electr. & Comput. Eng., Virginia Polytech. Inst. & State Univ., USA
fYear
2002
fDate
25-28 Sept. 2002
Firstpage
251
Lastpage
255
Abstract
A new architecture for power and area efficient RAKE receivers for a third generation wireless WCDMA system is presented. The proposed approach based on parallel operations of code generators eliminates de-skew blocks of RAKE receivers and shares several blocks such that compensators, orthogonal variable spreading factor code generators and scrambling code generators are shared among all fingers, which leads to power and area reduction. When the proposed architecture is applied to a RAKE receiver with four fingers, it reduces power dissipation by 55.2% and the area by 38.1% without any system performance degradation.
Keywords
3G mobile communication; CMOS integrated circuits; code division multiple access; compensation; integrated circuit design; low-power electronics; parallel architectures; radio receivers; CMOS technology; RAKE receiver fingers; block sharing; compensators; de-skew blocks; low-power area efficient RAKE receiver design; orthogonal variable spreading factor code generators; parallel RAKE receiver architecture; parallel code generator operation; performance degradation; power dissipation; scrambling code generators; third generation wireless WCDMA system; Correlators; Degradation; Fading; Fingers; Frequency; Multiaccess communication; Multipath channels; Power dissipation; Power generation; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC/SOC Conference, 2002. 15th Annual IEEE International
Print_ISBN
0-7803-7494-0
Type
conf
DOI
10.1109/ASIC.2002.1158066
Filename
1158066
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