Design of a shared buffer management scheme for ATM switches

This paper presents a novel memory management scheme for a shared buffer ATM switch that features low cost, high throughput, and high memory utilization. The design approach is based on the dual-port RAM device which can improve the memory bandwidth and reduce the complex address control of the shared buffer. In addition, the proposed memory management scheme adopts a temporary-point approach to improve the conventional bubble elimination design. The temporary-point approach eliminates the bubble problem of the linked list chain, and also achieves double throughput performance compared with the conventional single-port RAM shared buffer architecture. The whole design was fabricated with the TSMC 0.35 μm SPQM CMOS process parameters under 3.3 V supply voltage. With a 256 cell shared buffer architecture, the measured results show that both the cell-writing process and cell-reading process of this chip worked in parallel with speeds up to 25 MHz.