An innovative simulation approach for labs in computer architecture

This paper describes a new approach to lab assignments in computer architecture courses. Using a tool suite for the target instruction-set architecture, students model the performance of a sequence of processor architectures running selected benchmark programs. Students add code to a fully functional emulator to track the timing of each instruction based on the data and hardware resources it requires. By comparing the needs of the current instruction with records of resource usage and result timing of prior instructions, it can be determined if this instruction must be delayed for any reason. This approach results in cycle-accurate timing without the overhead of models at the register-transfer level, and it illustrates how diverse architectural elements combine to make a processor work. Students verify their code by matching the results of a standard, and then they use their simulators to study the performance tradeoffs of a variety of high-level design alternatives.