• DocumentCode
    387613
  • Title

    A novel framework for multilevel routing considering routability and performance

  • Author

    Lin, Shih-Ping ; Chang, Yao-Wen

  • Author_Institution
    Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
  • fYear
    2002
  • fDate
    10-14 Nov. 2002
  • Firstpage
    44
  • Lastpage
    50
  • Abstract
    We propose in this paper a novel framework for multilevel routing considering both routability and performance. The two-stage multilevel framework consists of coarsening followed by uncoarsening. Unlike the previous multilevel routing, we integrate global routing, detailed routing, and resource estimation together at each level of the framework, leading to more accurate routing resource estimation during coarsening and thus facilitating the solution refinement during uncoarsening. Furthermore, the exact routing information obtained at each level makes our framework more flexible in dealing with various routing objectives (such as crosstalk, power, etc). Experimental results show that our approach obtains significantly better routing solutions than previous works. For example, for a set of 11 commonly used benchmark circuits, our approach achieves 100% routing completion for all circuits while the previous multilevel routing, the three-level routing, and the hierarchical routing can complete routing for only 3, 0, and 3 circuits, respectively. In particular, the number of routing layers used by our router is even smaller. We also have performed experiments on timing-driven routing. The results are also very promising.
  • Keywords
    VLSI; circuit layout CAD; circuit simulation; crosstalk; integrated circuit layout; network routing; network topology; parameter estimation; timing; benchmark circuits; coarsening; crosstalk; detailed routing; global routing; hierarchical routing; level routing information; multilevel routing framework; routability; routing completion; routing layers; routing resource estimation; three-level routing; timing-driven routing; two-stage framework; uncoarsening; Circuits; Costs; Crosstalk; Integer linear programming; Nonhomogeneous media; Partitioning algorithms; Routing; Scalability; Tiles; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Aided Design, 2002. ICCAD 2002. IEEE/ACM International Conference on
  • ISSN
    1092-3152
  • Print_ISBN
    0-7803-7607-2
  • Type

    conf

  • DOI
    10.1109/ICCAD.2002.1167512
  • Filename
    1167512