DocumentCode
387624
Title
Characteristic faults and spectral information for logic BIST
Author
Chen, Xiaoding ; Hsiao, Michael S.
Author_Institution
Bradley Dept. of Electr. & Comput. Eng., Virginia Tech., Blacksburg, VA, USA
fYear
2002
fDate
10-14 Nov. 2002
Firstpage
294
Lastpage
298
Abstract
We present a new method of built-in-self-test (BIST) for sequential circuits and system-on-a-chip (SOC) using characteristic faults and circuit-specific spectral information in the form of one or more Hadamard coefficients. The Hadamard coefficients are extracted from the test sequences for a small set of characteristic faults of the circuit. By extracting a few characteristic faults from the circuit, we show that detection of these characteristic faults is sufficient in detecting a vast majority of the remaining faults in the circuit. The small number of characteristic faults allows us to reduce the coefficients necessary for BIST. State relaxation is performed on the compacted test sequences to reduce the spectral noise further. Since we are targeting only a very small number of characteristic faults, the execution times for computing the spectra are greatly reduced. Our experimental results show that our new method can achieve high BIST coverage with both lower computational efforts and storage, with very few characteristic faults.
Keywords
Hadamard transforms; built-in self test; fault location; integrated circuit design; integrated circuit testing; logic design; logic testing; sequential circuits; spectral analysis; system-on-chip; Hadamard coefficients/transforms; SOC; built-in-self-test; circuit-specific spectral information; compacted test sequences; fault detection; high BIST coverage; logic BIST characteristic faults; sequential circuit state relaxation; small characteristic fault set; spectra computation times/storage requirements; spectral noise reduction; system-on-a-chip; test sequences; Built-in self-test; Circuit faults; Circuit testing; Data mining; Electrical fault detection; Fault detection; Logic; Performance evaluation; Sequential circuits; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Aided Design, 2002. ICCAD 2002. IEEE/ACM International Conference on
ISSN
1092-3152
Print_ISBN
0-7803-7607-2
Type
conf
DOI
10.1109/ICCAD.2002.1167549
Filename
1167549
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