• DocumentCode
    387641
  • Title

    SAT and ATPG: Boolean engines for formal hardware verification

  • Author

    Biere, Armin ; Kunz, Worfgng

  • Author_Institution
    Dept. of Comput. Sci., Eidgenossische Tech. Hochschule, Zurich, Switzerland
  • fYear
    2002
  • fDate
    10-14 Nov. 2002
  • Firstpage
    782
  • Lastpage
    785
  • Abstract
    In this survey, we outline basic SAT- and ATPG-procedures as well as their applications in formal hardware verification. We attempt to give a path through the literature and provide a basic orientation concerning the problem formulations and known approaches in this active field of research.
  • Keywords
    Boolean functions; automatic test pattern generation; circuit analysis computing; computability; formal verification; ATPG; Boolean engines; SAT; combinational equivalence checking; conjunctive normal form; formal hardware verification; property checking; satisfiability; Application software; Automatic test pattern generation; Circuit faults; Circuit testing; Computer science; Electronic design automation and methodology; Engines; Equations; Fault location; Hardware;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Aided Design, 2002. ICCAD 2002. IEEE/ACM International Conference on
  • ISSN
    1092-3152
  • Print_ISBN
    0-7803-7607-2
  • Type

    conf

  • DOI
    10.1109/ICCAD.2002.1167620
  • Filename
    1167620
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=387641