VLSI Implementation of a linear systolic array

Linear systolic arrays are well known examples of a concurrent systems approach which provides the potential for high performance and flexibility without attendant design complexity[1]. Generally such arrays take problems of O(n²) complexity and provide the solution in O(n) time steps using O(n) processors, where n is the order of the system (number of unknowns or filter poles). Although much work has been done defining the capabilities of such an array [2], very few have been built [3,4,5]. We describe here an operational prototype linear systolic array that uses a custom designed VLSI chip for modularity, high performance and design simplicity. We also describe a few applications examples, with emphasis on Toeplitz linear systems, to illustrate its operation.