A bit-serial VLSI vector quantizer

A VLSI architecture for a mean residual reflected vector quantizer (MRRVQ) is presented which uses bit and word level pipelining to increase throughput. The tradeoffs between silicon area and processing speed are described along with two different architectures for implementing the vector quantizer algorithm. Throughputs for the architectures range from 450,000 vectors per second down to 28,000 vectors per second assuming a 10MHz clock rate. The chips were designed and implemented using a VLSI design methodology known as Structured Tiling (ST) which reduced the required design time to under three man-months including only two weeks for layout.