Parallel VLSI computing array implementation for signal subspace updating algorithm

This paper concerns the parallel VLSI computing array implementaion for a novel signal subspace iteration algorithm (SSIA) proposed by Karasalo. Specifically, by making use of a sparse structure, a Linearly Connected VLSI computing structure is developed for the Singular Value Decomposition (SVD) operation employed in this algorithm. We first show that by making use of a sparse structue matrix the computing time of this algorithm can be reduced from O(N³) to O(N²) with single processors. Then we show that the parallel architecture is able to reduce the overall computing time for SVD from O(N²) to O(N) using O(N) processors. Where N is the dimension of the signal subspace. This makes the total computing time of SSIA from max(O(K²) O(N²K)) with single processors to O(K) with O(N²) processors.