Bit serial systolic chip set for real-time image coding

The implementation of real-time image encoding requires a high and constant throughput rate not achievable by a SISD machine. With a reasonable size codebook and SIMD machine architecture. Vector Quantization algorithm can be implemented in real-time. But, single stage Vector Quantization requires fairly large-size codebook for good quality image encoding. Multi-Stage Vector Quantization with codebooks of moderate size at each stage has been shown to be an alternative viable approach. The bits per pixel rates for TV quality composite color image encoding using Multi-Stage Vector Quantization are reported. The VQ/MSVQ implementation requires two processors, inner product processor and comparator-address generator. The implementation details of the processors and their throughput rate are described.