An error anaylsis of a FFT implementation using the residue number system

This paper considers an implementation of the FFT based upon the residue number system. This system offers the advantages of using integer based arithmetic operations and a simple hardware realization involving table look-up arrays. The proposed architecture is such that rapid evolutionary changes in read-only-memory technology can be easily incorporated into the hardware realization. In this paper, a generalized expression for predicting RMS relative error that includes A/D quantization, integer normalization and scaling rounding considerations, has been derived. This analysis leads to the optimal choice of several parameters, which are related to error minimization and simplification of the hardware realization. The generalized expression derived with respect to the FFT can also be used to predict errors in high-speed convolution filters.