Architecture for a real-time LPC-based feature measurement integrated circuit

An architecture for an integrated circuit to perform LPC-based feature measurement in real time has been developed for speech recognition applications. The integrated circuit architecture is suitable for both isolated word recognition, in which the pattern matching occurs after the end of the utterance, and connected word recognition, where the pattern matching proceeds in synchrony with the speech input. A major feature of this architecture is the presence of stored program control which implements the LPC-based feature extraction algorithm on a single set of computational resources. Preliminary timing analysis indicates that a portion of real time remains unused. Thus, in addition to performing standard LPC-based feature analysis in real time, through program modification and memory addition, the architecture is expected to support more advanced concepts in speech recognition such as vector quantization. To aid in program development, software tools which include an assembler and a simulator and run on the UNIX* operating system have been developed. The projected chip complexity is approximately 20,000 transistors of random logic, 40,000 bits of ROM, and 2,500 bits of RAM.