A CMOS-VLSI rate conversion digital filter for digital audio signal processing

This paper describes CMOS-VLSI architecture for a rate conversion digital filter which interpolates an input discrete-time audio signal at the twice times higher sampling rate. In the proposed architecture, two discrete-time audio signals with 16-bit word length are multiplexed into a serial bit stream and are simultaneously interpolated through parallel table look up array multiplications. Based on the architecture study, the VLSI interpolator which contains 34,000 transistors has been fabricated with 3 µm CMOS technologies. Its power consumption is less than 100 mW and the maximum input sampling rate is 50 kHz. The interpolator quality is specified in terms of in-band amplitude ripple and out-band attenuation each of which is ± 0.13 dB or 80 dB, respectively.