Characterizing VeSFET-Based ICs With CMOS-Oriented EDA Infrastructure

Author

Xiang Qiu ; Marek-Sadowska, Malgorzata ; Maly, Wojciech P.

Author_Institution

Univ. of California, Santa Barbara, Santa Barbara, CA, USA

Volume

33

Issue

4

fYear

2014

fDate

Apr-14

Firstpage

495

Lastpage

506

Abstract

In this paper, we demonstrate that standard cell design methodology can be applied to design vertical slit field effect transistor (VeSFET)-based ASICs with modern CMOS EDA tools. We study a family of VeSFET canvases-chain canvases that improve performance and power consumption of circuits mapped to them compared to circuits implemented with VeSFET canvases composed of isolated transistors. We compare the designs implemented with a commercial low power CMOS library and corresponding VeSFET libraries. VeSFET-based designs demonstrate significant power reduction as compared to the CMOS-based designs at the same performance.

Keywords

CMOS integrated circuits; application specific integrated circuits; electronic design automation; field effect transistors; integrated circuit design; CMOS EDA tools; CMOS-based designs; CMOS-oriented EDA Infrastructure; VeSFET canvases; VeSFET-based ASICs; isolated transistors; low power CMOS library; power consumption; power reduction; standard cell design methodology; vertical slit field effect transistor; CMOS integrated circuits; Layout; Logic gates; Routing; Standards; Transistors; Wires; Canvas; EDA infrastructure; VeSFET; VeSTICs; junctionless; low cost transistor; low energy; low power; low volume ASICs; regular layout; twin-gate;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/TCAD.2013.2293539

Filename

6774532