• DocumentCode
    389467
  • Title

    A simulated annealing technique for multi-route cluster tools

  • Author

    Rostami, Shadi ; Hamidzadeh, Babak

  • Author_Institution
    Dept. of Electr. & Comput. Eng., British Columbia Univ., Canada
  • Volume
    7
  • fYear
    2002
  • fDate
    6-9 Oct. 2002
  • Abstract
    We provide scheduling techniques to enable cluster tools to produce different kinds of wafers at the same time. In this model, the multi-route model, wafers can visit different processing modules in their path. Some of these processing modules may have a limit on how long they allow the wafer to stay after the process is finished. If none of the modules have this timing constraint, we provide a greedy algorithm to schedule the multi-route cluster tool. However, if some modules have a timing constraint, the scheduling problem becomes more complicated, and an exhaustive search in a very large search space must be performed to find the optimal schedule. The exhaustive search may take as long as an hour to come up with the answer, and is not practical. We provide a simulated annealing technique to find a near-optimal schedule. To evaluate each state in the simulated annealing we need to solve a linear programming system. Instead of solving that LP system with conventional methods, we provide a much faster method. This method that uses shortest path algorithm and binary search improves the performance of the simulated annealing significantly. Our experiments showed that we can find a near-optimal solution in less than 2 minutes with this method.
  • Keywords
    flexible manufacturing systems; integrated circuit manufacture; linear programming; production control; simulated annealing; linear programming system; multi-route cluster tools; multi-route model; processing modules; scheduling techniques; simulated annealing; wafers; Computational modeling; Flexible manufacturing systems; Greedy algorithms; Job shop scheduling; Optimal scheduling; Processor scheduling; Semiconductor device manufacture; Semiconductor device modeling; Simulated annealing; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Systems, Man and Cybernetics, 2002 IEEE International Conference on
  • ISSN
    1062-922X
  • Print_ISBN
    0-7803-7437-1
  • Type

    conf

  • DOI
    10.1109/ICSMC.2002.1175710
  • Filename
    1175710