• DocumentCode
    389951
  • Title

    A compact DSP for audio codecs applications with multi-rate programmable filtering enhancement

  • Author

    Sharifkhani, M. ; Golampoor, I. ; Shoaei, O.

  • Author_Institution
    Dubai Design Center, Valence Semicond., Dubai, United Arab Emirates
  • Volume
    2
  • fYear
    2002
  • fDate
    29 June-1 July 2002
  • Firstpage
    1515
  • Abstract
    A compact signal processing architecture using a Nested Canonical Signed Digit (CSD)-Multiplier is described in this paper. The signal processor is a suitable solution for various kinds of filtering for two path purposes. The DSP could be used as a core without any basic changes for multi-channel applications with higher clock rates. It takes 0.35 mm2 (RAM and ROM excluded) in a 0.35 um CMOS library.
  • Keywords
    CMOS digital integrated circuits; digital signal processing chips; filtering theory; multiplying circuits; programmable filters; speech codecs; 0.35 micron; CMOS DSP; Nested Canonical Signed Digit Multiplier; audio codec; digital signal processing; multi-rate programmable filtering; Arithmetic; Clocks; Codecs; Digital signal processing; Filtering; Filters; Phase change materials; Read only memory; Signal processing; Signal processing algorithms;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Communications, Circuits and Systems and West Sino Expositions, IEEE 2002 International Conference on
  • Print_ISBN
    0-7803-7547-5
  • Type

    conf

  • DOI
    10.1109/ICCCAS.2002.1179066
  • Filename
    1179066
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=389951