Title :
An interleaved round-robin scheduling chip for 1.2 G-bps ATM networking
Author :
Chu, Yuan-Sun ; Li, Chi-Fang ; Chiu, Chih-Yang
Author_Institution :
Dept. of Electr. Eng., Nat. Chung Chen Univ., Ming-Hsiung, Taiwan
Abstract :
This paper proposes an interleaved round-robin (IRR) scheduling chip for providing good cell-delay-variation (CDV) performance in ATM networking. The chip is designed to carry out a multi-class IRR scheduling algorithm to support 256 connections with 8 classes concurrently. The multi-class method reduces its sorting complexity from 256 to 8. The chip has been fabricated by the TSMC 0.6-μm SPDM process. Its core size is 3.5×3.5 mm2 and power dissipation is 176-mW at 33 MHz. It is able to support a 1.2 Gbps ATM network.
Keywords :
CMOS digital integrated circuits; asynchronous transfer mode; integrated circuit layout; multiplexing equipment; scheduling; 0.6 micron; 1.2 Gbit/s; 176 mW; 33 MHz; ATM networking; CDV performance; IRR scheduling chip; TSMC SPDM process; cell-delay-variation performance; core size; interleaved round-robin scheduling chip; multi-class IRR scheduling algorithm; multi-class method; power dissipation; sorting complexity; Algorithm design and analysis; Asynchronous transfer mode; Bandwidth; Delay effects; Hardware; Jitter; Multiplexing; Quality of service; Scheduling algorithm; Sorting;
Conference_Titel :
TENCON '02. Proceedings. 2002 IEEE Region 10 Conference on Computers, Communications, Control and Power Engineering
Print_ISBN :
0-7803-7490-8
DOI :
10.1109/TENCON.2002.1180243
